1. Field of the Invention. This invention relates to packaging techniques for integrated circuits and more particularly to techniques for providing power and ground planes for making connections to an integrated-circuit die.
2. Prior Art. The footprint, or area, of a semiconductor package with a high I/O lead count is generally much larger than the footprint of the silicon integrated-circuit die contained in the package. The leadframe provides an interface between the I/O pins for the package, which may be several hundred in number, and the corresponding bonding pads on the periphery of the integrated-circuit die. A leadframe functions to converge a large number of conductors in the leadframe into a small area near the die itself. Because of the leadframe geometry restrictions, the size of the leads and the spacing between the leads are small. Bonding fingers are provided on the leadframe adjacent to the integrated-circuit die for connection of the leads of the leadframe to the bonding pads on the integrated-circuit die. The inductance (typically 10-20 nanohenrys) of the bonding wires used for interconnecting the die to the bonding fingers of the leadframe often limits the electrical performance of the integrated-circuit package, particularly for distribution of power and ground, where problems of groundbounce and conducted interference degrade operation of the integrated circuits on the die.
One solution to this problem is to provide large low-inductance conductive planes in a multi-layer chipcarrier package configuration. Several conductive planes are provided within the base of the package and conductive vias provide connections to the various planes. Fabrication of this type of multi-layers and vias are expensive. An inexpensive solution which includes a low cost molded-plastic epoxy package design to obtain improved power-distribution performance is needed.